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IRFB11N50A, SiHFB11N50A
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 52 13 18 Single
D
FEATURES
500 0.52
* Low Gate Charge Qg Results in Simple Drive Requirement * Improved Gate, Avalanche and Dynamic dV/dt Ruggedness * Fully Characterized Capacitance and Avalanche Voltage and current * Lead (Pb)-free Available
Available
RoHS*
COMPLIANT
APPLICATIONS
* Switch Mode Power Supply (SMPS) * Uninterruptible Power Supply * High Speed Power Switching
TO-220
G
APPLICABLE OFF LINE SMPS TOPOLOGIES
S G D S N-Channel MOSFET
* Two Transistor Forward * Half and Full Bridge * Power Factor Correction Boost
ORDERING INFORMATION
Package Lead (Pb)-free SnPb TO-220 IRFB11N50APbF SiHFB11N50A-E3 IRFB11N50A SiHFB11N50A
ABSOLUTE MAXIMUM RATINGS TC = 25 C, unless otherwise noted
PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque for 10 s 6-32 or M3 screw TC = 25 C EAS IAR EAR PD dV/dt TJ, Tstg VGS at 10 V TC = 25 C TC = 100 C SYMBOL VDS VGS ID IDM LIMIT 500 30 11 7.0 44 1.3 275 11 17 170 6.9 - 55 to + 150 300d 10 1.1 W/C mJ A mJ W V/ns C lbf * in N*m A UNIT V
Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 C, L = 4.5 mH, RG = 25 , IAS = 11 A (see fig. 12). c. ISD 11 A, dI/dt 140 A/s, VDD VDS, TJ 150 C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91094 S-81243-Rev. B, 21-Jul-08 www.vishay.com 1
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
THERMAL RESISTANCE
PARAMETER Maximum Junction-to-Ambient Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain) SYMBOL RthJA RthCS RthJC TYP. 0.50 MAX. 62 0.75 C/W UNIT
SPECIFICATIONS TJ = 25 C, unless otherwise noted
PARAMETER Static Drain-Source Breakdown Voltage Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode
D
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS VGS(th) IGSS IDSS RDS(on) gfs
VGS = 0 V, ID = 250 A VDS = VGS, ID = 250 A VGS = 30 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 150 C VGS = 10 V ID = 6.6 Ab VDS = 50 V, ID = 6.6 A VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VDS = 1.0 V, f = 1.0 MHz VGS = 0 V VDS = 400 V, f = 1.0 MHz VDS = 0 V to 400 V ID = 11 A, VDS = 400 V see fig. 6 and 13b
500 2.0 6.1
-
4.0 100 25 250 0.52 -
V V nA A S
Ciss Coss Crss Coss Coss eff. Qg Qgs Qgd td(on) tr td(off) tf VGS = 10 V
-
1423 208 8.1 2000 55 97 14 35 32 28
52 13 18 ns nC pF
VDD = 250 V, ID = 11 A RG = 9.1 , RD = 22 , see fig. 10b
-
-
510 3.4
11 A 44 1.5 770 5.1 V ns C
G
S
TJ = 25 C, IS = 11 A, VGS = 0 Vb TJ = 25 C, IF = 11 A, dI/dt = 100 A/sb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 s; duty cycle 2 %. c. Coss effective is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
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Document Number: 91094 S-81243-Rev. B, 21-Jul-08
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 C, unless otherwise noted
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
100
I D , Drain-to-Source Current (A)
10
I D , Drain-to-Source Current (A)
10
TJ = 150 C TJ = 25 C
1
1
0.1 0.1
4.5V 20s PULSE WIDTH TJ = 25 C
1 10 100
0.1 4.0
V DS = 50V 20s PULSE WIDTH 5.0 6.0 7.0 8.0 9.0
VDS , Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
VGS , Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
100
TOP
RDS(on) , Drain-to-Source On Resistance (Normalized)
I D , Drain-to-Source Current (A)
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V
3.0
ID = 11A
2.5
2.0
10
1.5
1.0
0.5
4.5V
1 1 10
20s PULSE WIDTH TJ = 150 C
100
0.0 -60 -40 -20
VGS = 10V
0 20 40 60 80 100 120 140 160
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
TJ , Junction Temperature ( C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91094 S-81243-Rev. B, 21-Jul-08
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IRFB11N50A, SiHFB11N50A
Vishay Siliconix
2400
2000
C, Capacitance (pF)
iss
1600
ISD , Reverse Drain Current (A)
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd
100
10
oss
1200
TJ = 150 C
800
1
TJ = 25 C
rss
400
0 1 10 100 1000
A
0.1 0.0
V GS = 0 V
0.4 0.8 1.2 1.6
VDS , Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
VSD ,Source-to-Drain Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
20
ID = 6.6A VDS = 400V VDS = 250V VDS = 100V
1000
VGS , Gate-to-Source Voltage (V)
OPERATION IN THIS AREA LIMITED BY RDS(on)
16
ID , Drain Current (A)
100 10us 10 100us 1ms 1 10ms
12
8
4
0 0 10 20
FOR TEST CIRCUIT SEE FIGURE 13
30 40 50
0.1
TC = 25 C TJ = 150 C Single Pulse
10 100 1000 10000
QG , Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
VDS, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
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Document Number: 91094 S-81243-Rev. B, 21-Jul-08
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
RD
12
VGS
VDS
10
D.U.T.
+
RG
ID , Drain Current (A)
- VDD
8
10V
Pulse Width 1 s Duty Factor 0.1 %
6
Fig. 10a - Switching Time Test Circuit
4
VDS
2
90 %
0 25 50 75 100 125 150
10 % VGS t d(on) tr t d(off) t f
TC , Case Temperature ( C)
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
1
Thermal Response (Z thJC )
D = 0.50
0.20 0.1 0.10 0.05 0.02 0.01 PDM t1 SINGLE PULSE (THERMAL RESPONSE) t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.001 0.01 0.1 1
0.01 0.00001
0.0001
t1 , Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
V DS
15 V
tp
VDS
L
Driver
RG 20 V tp
D.U.T. IAS 0.01
+ A - VDD
A
I AS
Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91094 S-81243-Rev. B, 21-Jul-08
Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
EAS , Single Pulse Avalanche Energy (mJ)
600
TOP
500
BOTTOM
ID 4.9A 7.0A 11A
10 V QGS
QG
400
Q GD
300
VG
200
Charge
100
Fig. 13a - Basic Gate Charge Waveform
0 25 50 75 100 125 150
Current regulator Same type as D.U.T.
Starting TJ , Junction Temperature ( C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
50 k 12 V 0.2 F 0.3 F
660
D.U.T.
+ V - DS
V DSav , Avalanche Voltage (V)
VGS
640
3 mA
IG
620
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
600
580 0.0
A
1.0 2.0 3.0 4.0 5.0 6.0 7.0
I av , Avalanche Current (A)
Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanche Current
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Document Number: 91094 S-81243-Rev. B, 21-Jul-08
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T
+
Circuit layout considerations * Low stray inductance * Ground plane * Low leakage inductance current transformer
+ +
-
RG
* * * *
dV/dt controlled by R G Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test
+ VDD
Driver gate drive P.W. Period D=
P.W. Period VGS = 10 V*
D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt
VDD
Re-applied voltage Inductor current
Body diode
forward drop
Ripple 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91094.
Document Number: 91094 S-81243-Rev. B, 21-Jul-08
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Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000 Revision: 18-Jul-08
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